The present invention relates to method and apparatus for logic simulation to be used for verifying an operation of a logic circuit, and more particularly to method and apparatus for event driven logic simulation.
More specifically, the present invention relates to method and apparatus for logic simulation in which a change in a signal status at an input terminal or a change in a signal status at an output terminal of an element of a logic circuit to be simulated (a gate such as AND, NAND, OR, NOR or XOR, a memory such as RAM or ROM, a functional element such as flip-flop, counter or gate array, a bilateral element realized by MOS transistors, or a virtual element representing a bus) is considered as an event, and the signal status at the output terminal is calculated only for that element whose signal status at the input terminal has changed.
Prior art method and apparatus for logic simulation are explained with reference to FIG. 22 which shows a schematic configuration of a conventional event driven logic simulation apparatus. In FIG. 22, numeral 221 denotes a current time output unit, numeral 222 denotes an event memory, numeral 223 denotes an event take-out unit, numeral 224 denotes a circuit operation calculation unit, and numerals 826, 827, 828, 829, 830, 831 and 832 denote signal lines.
Simulation is carried out by transferring the event among the event memory 222, event take-up unit 23 and circuit operation calculation unit 224.
The current time output unit 221 is initially set to "0" and outputs a current time on the signal line 826.
The event memory 222 stores those events whose event times are equal to or larger than the current time.
The event take-out unit 223 takes out an event whose event time is equal to the current time from the event memory 222 through the signal line 827 and outputs it on the signal line 828.
The circuit operation calculation unit 224 receives the event from the signal line 828, calculates new changes in the signal status at the input terminal and the output terminal of the element in the logic circuit to be simulated, which changes are caused by a change in a signal status represented by the event, in accordance with the event driven algorithm, and outputs the event representing the result of calculation on the signal line 829.
The event memory 222 receives the event from the signal line 829 and stores it.
The current time output unit 221 is informed from the event memory 222 through the signal line 832 whether events whose event times are equal to the current time are present in the event memory 222, informed from the event take-out unit 223 through the signal line 830 whether an event is present in the event take-out unit 223, informed from the circuit operation calculation unit 224 through the signal line 831 whether an event is present in the circuit operation calculation unit 224, and when there is no event having the event time equal to the current time in the event memory 222 and there is no event in either the event take-out unit 223 or the circuit operation calculation unit 224, the current time output unit 221 determines that all processes for the current time have been completed and it advances the current time.
Then, the above processes are repeated for the new current time so that the simulation is proceeded.
Recently, such a logic simulation apparatus is realized by hardware and the event memory 222, event take-out unit 223 and circuit operation calculation unit 224 are pipelined or the circuit operation calculation unit 224 itself is further pipelined in order to attain a high speed in the simulation.
However, in the prior art logic simulation method, that is, the event driven logic simulation method in which the current time is advanced after all events in the event take-out unit and the circuit operation calculation unit have been processed, if a logic simulation apparatus for performing the simulation in accordance with the above simulation method is provided to effect pipeline processing by the event memory, event take-out unit and circuit operation calculation unit, it is necessary to store all events in the event memory. As a result, the increase of the processing speed by the pipeline processing is not substantial.
The high speed operation by the pipeline processing is explained in general with reference to FIGS. 20 and 21 which illustrate the pipeline processing. In FIG. 20, A, B and C denote processors which constitute a pipeline, and n-2, n-1, n, n+1 and n+2 denote data. In FIG. 21, A, B and C denote processors which constitute the pipeline, and n-2, n-1, n+1 and n+2 denote data.
It is assumed that the pipeline comprises three processors A, B and C which perform a series of processings. Each of the processors A, B and C can process one data in a unit time. If the processors A, B and C are not pipelined and the data are serially processed, three units of processing time are required for each data. By the pipeline processing, the processing speed may be increased. As shown in FIG. 20, it is assumed that at a time t, the data n is processed by the processor A, the data n-1 is processed by the processor B and the data n-2 is processed by the processor C. At a time t+1, the new data n+1 is processed by the processor A, the data n is processed by the processor B and the data n-1 is processed by the processor C. At a time t+2, the new data n+2 is processed by the processor A, the data n+1 is processed by the processor B and the data n is processed by the processor C.
Thus, in the pipeline processing, the three data n-2, n-1 and n are outputted from the pipeline in the three units of times t, t+1 and t+2. Thus, one data is processed in one unit time as a whole, and the processing speed is three times as high as that of the serial processing.
However, if the data are not continuously supplied from the external and there is no data to be processed in one of the processors in the pipeline, the degree of high speed operation of the pipeline processing decreases. As shown in FIG. 21, it is assumed that at a time t, the data n-1 is processed by the processor B and the data n-2 is processed by the processor C, but there is no data to be processed in the processor A. At the time t+1, the new data n+1 is processed by the processor A and the data n-1 is processed by the processor C, but there is no data to be processed in the processor B. At the time t+2, the new data n+2 is processed by the processor A and the data n+1 is processed by the processor B, but there is no data to be processed in the processor C. Thus, the two data n-2 and n-1 are outputted in the three units of times t, t+1 and t+2, and as a whole, one data is processed in 1.5 unit time.
Thus, if there is no data to be processed in one of the processors in the pipeline (a gap in the pipeline) or there is no data to be processed in the pipeline (vacancy in the pipeline), the degree of high speed operation by the pipeline processing is lowered.
Accordingly, in order to fully accomplish the high speed operation by the pipeline processing, it is necessary to continuously supply the data to the pipeline.
However, in the prior art event driven logic simulation method in which the current time is advanced after all events in the event take-out unit and the circuit operation calculation unit have been processed, the update of the current time by the current time output unit and the take-out of the event having the new event time by the event take-out unit must be carried out after the event take-out unit has taken out all events having the equal event time to the current time from the event memory and the circuit operation calculation unit has processed all such events. Thus, the two processors, that is, the vent take-out unit and the circuit operation calculation unit of the pipeline which comprises the event memory, event take-out unit and circuit operation calculation unit must be emptied.
As a result, where the prior art method in which the current time is advanced after the events in the event take-out unit and the circuit operation calculation unit have been emptied is used, the degree of high speed operation by the pipeline processing is lowered even if the logic simulation apparatus for the pipeline processing is prepared.